As known in the art, n-channel and p-channel MOS transistors can be connected together to form complementary MOS (CMOS) circuits, and these can be connected together with bipolar transistors to form BiCMOS circuits. In the art of the fabrication of these integrated circuits, the crucial linewidth feature is the uniformity of the source-drain lengths of the gate electrodes of the MOS (metal oxide semiconductor) transistors and of the widths of the emitter regions for the bipolar transistors, as well as the smoothness of the sidewalls of these electrodes.
In prior art, these electrodes are typically fabricated by (1) depositing a layer of the electrode material, (2) coating the layer of electrode material with a photoresist layer, (3) patterning the photoresist in accordance with the desired pattern of the transistor electrode, and (4) selectively etching the layer of electrode material using the remaining (patterned) layer of photoresist as an etch mask, whereby the electrode material remains only at areas located underneath the patterned photoresist. Hence the remaining electrode material can serve as the desired electrode for the bipolar or MOS transistor, as the case may be.
This (positive tone) method, however, suffers from a disadvantage that is especially undesirable in case the width (feature size) of the electrode is less than approximately 0.6 micrometer, namely, the disadvantage that the uniformity of the electrode widths from wafer to wafer or from batch of wafers to batch of wafers, or both, may not be good enough at such small feature sizes for commercially acceptable yields. By "wafer to wafer" uniformity is meant the uniformity of one semiconductor wafer relative to another wafer being simultaneously fabricated; by "batch to batch" uniformity is meant the uniformity of one group of semiconductor wafers being fabricated relative to another. More specifically, this nonuniformity arises from the fact that the sidewalls of the electrodes, as well as the lengths of the electrodes, as fabricated by the above-described positive tone method are not well controlled, since the etching of an electrode fluctuates with the parameters of its deposition and doping. Also a so-called "proximity effect" can occur. This effect arises from the fact that debris from each electrode being etched is deposited at the edges of neighboring electrodes, whereby the presence of each electrode can undesirably influence the dimensions of the neighboring electrodes in an irregular and uncontrolled manner. Moreover, photoresist layers with feature sizes below approximately 0.6 micrometer can have an unwantedtendency to distort (because of stress), to lift at the edges (undercut), or to peel off (lift off) prematurely, i.e., to peel off before serving their function as masks against etching the electrode material located underneath these photoresist layers, whereby the contours of the electrode edges are distorted.
Furthermore, in fabricating transistors of the bipolar type, self-aligned base contact structures are desirable. That is, it is desirable (in a vertical transistor path structure) that the emitter-base junction should automatically be laterally confined to within a relatively small distance from the lateral extent of the highly doped base contact. In U.S. Pat. No. 4,824,796, such a self-aligned base contact structure in a bipolar transistor was described, but fabrication of that structure required a step of etching into the silicon substrate in the base contact region. Such a step undesirably requires extremely careful control over the etching time, lest the base contact diffusion extend too deeply into the collector region, or require the structure to have an undesirably thicker base.
Therefore it would be desirable to have a method for fabricating both gate and emitter electrodes for MOS and bipolar transistors, respectively, preferably both at the same time on the same semiconductor body, for both n channel and p channel MOS (BiCMOS) transistors, which alleviates the foregoing problems.